1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device (to be referred to as a BiMOS hereinafter) on which a bipolar transistor and a MOS transistor are formed together.
2. Description of the Related Art
A BiMOS technique is used for obtaining a high-speed LSI having low power consumption, in which a logic gate, formed by combining a high-speed bipolar transistor, and a highly integrated CMOS transistor, capable of reducing power consumption, are mounted on a single chip.
In the manufacture of a conventional BiMOS LSI, the gate material of NMOS and PMOS transistors is formed using n-type polysilicon, and an npn transistor is mainly used as the bipolar transistor. For this reason, the external base electrode of the npn bipolar transistor cannot be made of the same material as that of the gate electrode of the MOS transistor. Therefore, either the gate electrode or the external base electrode must be formed in advance.
In conventional BiMOS LSI, the gate electrode is formed first. After forming the gate electrode, source and drain diffusion layers are formed by ion implantation and annealing. An external base electrode is formed, and then a base diffusion layer is formed by annealing.
However, when the gate electrode is formed in advance as described above, during the manufacture of elements, an annealing process must be performed twice for the MOS transistor. As a result, the sizes of the source and drain diffusion layers are excessively increased, and the channel width is decreased, thereby generating a short channel effect. Sufficient annealing cannot then be applied when the base diffusion layer of the bipolar transistor is formed. For this reason, the base resistance between the underlying portion of the external base electrode and an emitter diffusion layer increases, thus degrading the characteristics of the device.